Overview

Clockless Logic research in the Computer Architecture Lab deals with Gate and Throughput Optimization of Self-timed Circuits. This research led to new clockless circuit synthesis and gate-level pipelining techniques, culminating in a delay-insensitive 32x32+72 bit Multiply-Accumulate unit with 2.48-fold throughput increase over previous designs. Timers and other functional circuits have also been designed and analyzed using the clockless NULL Convention Logic (NCL) paradigm from Theseus Logic Incorporated. NCL offers a self-timed logic paradigm where control is inherent with each datum. NCL follows the so-called "weak conditions" of Seitz's delay-insensitive signaling scheme. As with other self-timed logic methods, the NCL paradigm assumes that forks in wires within basic components are isochronic, but is insensitive to logic delays. Current research in this area is proceeding with self-resetting pipeline logic. Results appear in several journals and conferences, plus in various functional designs and library contributions to Theseus Logic Incorporated.

Sponsors

• Theseus Logic, Inc. [Sponsor's Site] [Award Details]
• UCF Presidential Research Infrastructure Initiative [Sponsor's Site] [Award Details]
• Some sponsors co-listed with UCF Chip Design and Reliability Lab (CDRL)

People

Faculty

Publications

Journal Articles

1. T. Kocak, G. R. Harris, R. F. DeMara, “Self-timed Architecture for Masked Successive Approximation Analog-to-Digital Conversion,” revision pending to Journal of Circuits, Systems and Computers, revised and resubmitted October 13, 2005.
   [abstract] [pdf]
2. J. Di, J. S. Yuan, and R. F. DeMara, “Improving Power-awareness of Pipelined Array Multipliers using 2-Dimensional Pipeline Gating and its Application to FIR Design,” Integration, the VLSI Journal, Vol. 39, No. 1, June, 2005, in-press.
   [abstract] [pdf] [doc] [bibtex]
3. S. C. Smith, R. F. DeMara, J. S. Yuan, D. Ferguson, and D. Lamb, “Optimization of NULL Convention Self-timed Circuits,” Integration, The VLSI Journal, Vol. 37, No. 3, August, 2004, pp. 135 – 165.
   [abstract] [pdf] [bibtex]
4. W. Kuang, J. S. Yuan, R. F. DeMara, M. Hagedorn, and K. Fant, “Performance Analysis and Optimization of NCL Self-timed Rings,” IEE Proceedings on Circuits, Devices, and Systems, Vol. 150, No. 3, June, 2003, pp. 167 – 172.
   [abstract] [pdf] [doc] [bibtex]
5. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “NULL Convention Multiply and Accumulate Unit with Conditional Rounding, Scaling, and Saturation,” Journal of Systems Architecture, Vol. 47, No. 12, June, 2002, pp. 977 – 998.
   [abstract] [pdf] [bibtex]
6. R. F. DeMara, R. Mercer, and M. Ebel, “Helical Latch for Scalable Boolean Logic Operations,” Nanotechnology, Vol. 5, No. 3, July, 1994, pp. 137 – 156.
   [abstract] [pdf] [bibtex]

Conference Proceedings

1. R. F. DeMara, A. Kejriwal, and J. R. Seeber, “Feedback Techniques for Dual-Rail Self-Timed Circuits,” in Proceedings of the 2004 International Conference on VLSI (VLSI-04), pp. 458 – 464, Las Vegas, Nevada, U.S.A., June 21 – 24, 2004.
   [abstract] [pdf] [doc] [ppt] [bibtex]
2. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “Speedup of Delay-Insensitive Digital Systems Using NULL Cycle Reduction,” in Proceedings of the 2001 International Workshop on Logic and Synthesis (IWLS’01), Granlibakken, California, U.S.A., pp. 185 – 189, June 12 – 15, 2001.
   [abstract] [pdf] [bibtex]
3. W. Kuang, J. S. Yuan, R. F. DeMara, D. Ferguson, and M. Hagedorn, “A Delay-insensitive FIR Filter for DSP Applications,” in Proceedings of the Ninth Annual NASA Symposium on VLSI Design, pp 2.2.1 – 2.2.7, Albuquerque, New Mexico, U.S.A., November 8 – 9, 2000.
   [abstract] [pdf] [bibtex]
4. N. Weng, J. S. Yuan, R. F. DeMara, D. Ferguson, and M. Hagedorn, “Glitch Power Reduction for Low Power IC Design,” in Proceedings of the Ninth Annual NASA Symposium on VLSI Design, pp. 7.5.1 – 7.5.7, Albuquerque, New Mexico, U.S.A., November 8 – 9, 2000.
   [abstract] [pdf] [doc] [bibtex]
5. R. N. Mercer, M. Ebel, and R. F. DeMara, “Pipelined Architecture for Computational Nanotechnology,” in Proceedings of the 1994 IEEE Southcon Conference (Southcon’94), pp. 314 – 319, Orlando, Florida, U.S.A., March 29 – 31, 1994.
   [abstract] [pdf] [bibtex]
6. R. Mercer, M. Ebel, and R. F. DeMara, “Helical Boolean Logic Elements,” in Proceedings of the Third Foresight Conference on Molecular Nanotechnology, Palo Alto, California, U.S.A., October 14 – 16, 1993.
   [abstract] [pdf] [bibtex]