Overview

Evolvable Hardware is a forward-looking field at the intersection of Computer Architecture and Intelligent Systems. It employs Field Programmable Gate Array (FPGA) devices which are SRAM-based components whose annual production exceeds 300 million chips. Each FPGA device provides a million gate-equivalent fabric that can be evolved in-situ within embedded applications. The FPGA logic fabric is adapted autonomously using search techniques based on Genetic Algorithms (GAs). The concept behind our research is that Evolvable Hardware can provide new paradigms for fault recovery. The Competitive Runtime Reconfiguration (CRR) approach that we developed leverages FPGAs’ inherent reconfigurability to evolve regenerated designs that avoid faulty resources. GA operators of crossover and mutation constructively evolve a refurbishment in response to specific failures, thus avoiding the weight and size associated with coarse-grained pre-designed spares. The project is analytically modeling the reconfigurability of on-chip resources using Markov Chains and Monte-Carlo Simulations during Year 1. During Year 2 and Year 3, we apply the results to develop a fully-functional prototype using a Xilinx Virtex-Pro FPGA to demonstrate self-repair. This is providing significant contributions to the fields of Evolvable Hardware and Fault Recovery because it is first to demonstrate functionality regeneration in-situ, in real-time, without synthetic test vectors, while allowing the device to remain partially online. A software-based simulation of the CRR procedure was successful and preliminary results were presented at recent conferences. An additional research component is on Voting Schemes for Evolutionary Repair in Reconfigurable Logic Devices. We are investigating 3-plex and 5-plex voting arrangements of partially-regenerated FPGA-based decoders and multipliers that can exhibit completely correct functionality.

Sponsors

• National Aeronautics and Space Administration (NASA) [Sponsor's Site] [Award Details]
• National Science Foundation (NSF) [Sponsor's Site] [Award Details]
• Some sponsors co-listed with UCF CRCD Project in Machine Learning

People

Faculty

Publications

Books

1. R. F. DeMara, editor, Advances in Evolvable Hardware, Studies in Computational Intelligence forthcoming, Springer-Verlag, 2005.
2. T. Plaks, R. F. DeMara, M. Gokhale, S. Guccione, M. Platzner, G. Smit, M. Wirthlin, editors, Proceedings of the Fifth International Conference on Engineering of Reconfigurable Systems and Algorithms, CSREA Press, 2005.

Book Chapters

1. J. D. Lohn, G. Larchev, and R. F. DeMara, "Fault Recovery and Correctness Evaluation of Sequential Circuits using Genetic Algorithms,"in Advances in Machine Learning, Springer Verlag Heidelberg (to appear).
   [abstract] [pdf] [doc] [bibtex]
2. J. D. Lohn, G. Larchev, and R. F. DeMara, “A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs,” in Lecture Notes in Computer Science, Springer-Verlag Heidelberg, 2003, ISSN: 0302-9743, pp. 47 – 56.
   [abstract] [pdf] [bibtex]
3. J. Castro, J. Secretan, M. Georgiopoulos, R. F. DeMara, G. Anagnostopoulos, and A. Gonzalez, "Pipelining Fuzzy ARTMAP without Match-Tracking," in Intelligent Engineering Systems through Artificial Neural Networks, Vol. 14, ASME Press, 2004, ISBN: 0-791-80228-0, pp. 100 - 106.
   [abstract] [pdf] [doc] [bibtex]

Journal Articles

1. Carthik A. Sharma, Ronald F. DeMara and Alireza Sarvi, “Self-Healing Reconfigurable Logic using Autonomous Group Testing,” submitted to ACM Transactions on Autonomous and Adaptive Systems (TAAS) of Special Issue on Organic Computing. May,2007.
   [abstract] [pdf] [doc] [bibtex]
2. Kening Zhang,Jaafar Alghzao, and R. F. DeMara, “Organic Embedded Architecture for Sustainable FPGA Soft-Core Processors,” submitted to ACM Transactions on Autonomous and Adaptive Systems (TAAS) of Special Issue on Organic Computing. May,2007.
   [abstract] [pdf] [doc] [bibtex]
3. Heng Tan,R. F. DeMara, “A Multi-layer Framework Supporting Autonomous Runtime Partial Reconfiguration,” submitted to IEEE Transactions Transactions on Very Large Scale Integration (VLSI) Systems on 2006.
   [abstract] [pdf] [bibtex]

Conference Proceedings

1. R. S. Oreifej, R. N. Al-Haddad, H. Tan and Ronald F. DeMara, "Layered Approach To Intrinsic Evolvable Hardware Using Direct Bitstream Manipulation Of Virtex II Pro Device," --"Best paper of session and nominated best of conference" in Proceedings of the 17th INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS (FPL'07), AMSTERDAM, NETHERLANDS, 27-29 AUGUST 2007, 2007.
   [abstract] [pdf] [doc] [ppt][bibtex]
2. R. S. Oreifej, C. A. Sharma, R. F. DeMara, "Expediting GA-Based Evolution Using Group Testing Techniques for Reconfigurable Hardware," in Proceedings of the IEEE International Conference on Reconfigurable Computing and FPGAs (Reconfig'06), San Luis Potosi, Mexico, September 20-22, 2006, pp 106-113.
   [abstract] [pdf] [doc] [ppt][bibtex]
3. H. Tan, R. F. DeMara, “A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration Overhead,” in Proceedings of the IEEE International Conference on Reconfigurable Computing and FPGAs (Reconfig’06), San Luis Potosi, Mexico, September 20 – 22, 2006, pp. 86-90.
   [abstract] [pdf] [doc][ppt] [bibtex]
4. K. Zhang, G. Bedette, R. F. DeMara, "Triple Modular Redundancy with Standby (TMRSB) Supporting Dynamic Resource Reconfiguration," in Proceedings of IEEE AUTOTESTCON 2006, September 18-21, 2006.
   [abstract] [pdf] [doc] [ppt] [bibtex]
5. H. Tan, R. F. DeMara, A. J. Thakkar, A. Ejnioui, J. D. Sattler, "Complexity and Performance Evaluation of Two Partial Reconfiguration Interfaces on FPGAs: a Case Study," in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'06), Las Vegas, Nevada, U.S.A, 2006.
   [abstract] [2-page pdf] [5-page pdf] [2-page doc] [5-page doc] [bibtex]
6. C. A. Sharma, R. F. DeMara, "A Combinatorial Group Testing Method for FPGA Fault Location", accepted to International Conference on Advances in Computer Science and Technology (ACST 2006), Puerto Vallarta, Mexico, January 23 - 25, 2006
   [abstract] [pdf] [doc][ppt] [bibtex]
7. C. J. Milliord, C. A. Sharma, R. F. DeMara, "Dynamic Voting Schemes to Enhance Evolutionary Repair in Reconfigurable Logic Devices," in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig'05), pp. 8.1.1 - 8.1.6, Puebla City, Mexico, September 28 - 30, 2005.
   [abstract] [pdf] [doc] [ppt] [bibtex]
8. K. Zhang, R. F. DeMara, C. A. Sharma, “Consensus-based Evaluation for Fault Isolation and On-line Evolutionary Regeneration,” in Proceedings of the International Conference in Evolvable Systems (ICES'05), pp. 12 - 24, Barcelona, Spain, September 12 - 14, 2005.
   [abstract] [pdf] [doc] [ppt] [bibtex]
9. R. F. DeMara and K. Zhang, “Autonomous FPGA Fault Handling through Competitive Runtime Reconfiguration,” in Proceedings of the NASA/DoD Conference on Evolvable Hardware(EH’05), Washington D.C., U.S.A., June 29 – July 1, 2005.
   [abstract] [pdf] [ppt] [bibtex]
10. H. Tan and R. F. DeMara, “A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’05), Las Vegas, Nevada, U.S.A, June 27 – 30, 2005.
    [abstract] [pdf] [ppt] [bibtex]
11. R. F. DeMara and C. A. Sharma, “Self-Checking Fault Detection using Discrepancy Mirrors,” in Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA’05), pp. 311-317, Las Vegas, Nevada, U.S.A, June 27 – 30, 2005.
    [abstract] [pdf] [ppt] [bibtex]
12. A. Ejnioui and R. F. DeMara, “Area Reclamation Metrics for SRAM-based Reconfigurable Device,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’05)), Las Vegas, Nevada, U.S.A, June 27 – 30, 2005.
    [abstract] [pdf] [ppt] [bibtex]
13. A. Ejnioui and R. F. DeMara, “FPGA Defragmentation for Sustainable Performance in Reconfigurable Computers,” in Proceedings of the International Symposium on VLSI (ISVLSI’05),Tampa, Florida, U.S.A., May 11 – 12, 2005.
    [abstract] [pdf] [doc] [bibtex]
14. M. Georgiopoulos, J. Castro, E. Gelenbe, R. F. DeMara, A. J. Gonzalez, M. Kysilka, M. Mollaghasemi, and A. S. Wu, "CRCD Experiences at the University of Central Florida: An NSF Project," in Proceedings of the 2004 American Society for Engineering Education Annual Conference and Exposition (ASEE’04), pp. 2432: 1 – 23, Salt Lake City, Utah, U.S.A., June 20 – 23, 2004.
    [abstract] [pdf] [bibtex]
15. J. Castro, M. Georgiopoulos, R. F. DeMara, and A. J. Gonzalez, “A Partitioned Fuzzy ARTMAP Implementation for Fast Processing of Large Databases on Sequential Machines,” in Proceedings of the Seventieth International Florida Artificial Intelligence Research Symposium (FLAIRS’04), Miami Beach, Florida, U.S.A., May 17 – 19, 2004.
    [abstract] [pdf] [bibtex]
16. M. Georgiopoulos, J. Castro, A. Wu, R. F. DeMara, E. Gelenbe, A. J. Gonzalez, M. Kysilka, and M. Mollaghasemi, “CRCD in Machine Learning at the University of Central Florida: Preliminary Experiences,” in Proceedings of the Eight Annual Conference on Innovation and Technology in Computer Science Education (ITiCSE-2003), pp. 249, Thessaloniki, Greece, June 30 – July 2, 2003.
    [abstract] [pdf] [bibtex]
17. M. Georgiopoulos, R. F. DeMara, E. Gelenbe, A. Gonzalez, M. Kysilka, M. Mollaghasemi, A. Wu, and I. Russell, “Machine Learning Advances for Engineering and Science Education: A CRCD Experience at the University of Central Florida”, in Proceedings of the Thirteenth International Conference on Artificial Neural Networks (ICANN’03), pp. 465 – 468, Istanbul, Turkey, June 26 – 29, 2003.
    [abstract] [pdf] [bibtex]
18. M. Georgiopoulos, I. Russell, J. Castro, A. Wu, M. Kysilka, R. F. DeMara, A. Gonzalez, E. Gelenbe, and M. Mollaghasemi, “A CRCD Experience: Integrating Machine Learning Concepts into Introductory Engineering and Science Programming Courses,” in Proceedings of the 2003 American Society for Engineering Education Annual Conference and Exposition (ASEE’03), pp. 1332: 1 – 20, Nashville, Tennessee, U.S.A., June 22 – 25, 2003.
    [abstract] [pdf] [bibtex]
19. J. D. Lohn, G. Larchev, and R. F. DeMara, “Evolutionary Fault Recovery in a Virtex FPGA Using a Representation that Incorporates Routing,” in Proceedings of the Seventieth International Parallel and Distributed Processing Symposium (IPDPS-2003) – Reconfigurable Architectures Workshop, pp. 172, Nice, France, April 22 – 26, 2003.
    [abstract] [pdf] [bibtex]
20. J. D. Lohn, G. Larchev, and R. F. DeMara, “A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs,” in Proceedings of the Fifth International Conference on Evolvable Systems (ICES’03), pp. 47 – 56, Trondheim, Norway, March 17 – 20, 2003.
    [abstract] [pdf] [bibtex]
21. J. D. Lohn and R. F. DeMara, “A Co-evolutionary Genetic Algorithm for Autonomous Fault-Handling in FPGAs,” in Proceedings of the Sixth International Conference on Military and Aerospace Programmable Logic Devices (MAPLD-2002), Laurel, Maryland, U.S.A., September 10 – 12, 2002.
    [abstract] [pdf] [bibtex]