Overview

Systems Architecture research in the Computer Architecture Lab spans the design of single and multiple processor architectures with an emphasis on memory systems and synchronization methods. Memory system research conducted includes design and analysis of Non-Uniform Memory Access (NUMA) architectures and their caching behavior, as well as interconnection strategies based on Multiport Memory devices. Hybrid SIMD/MIMD Architectures have also been developed based on parallel marker-propagation paradigms for real-time speaker-independent speech recognition utilizing these techniques.

Time and Space Efficient Barrier Synchronizationresearch includes theoretical models, software schemes, and dedicated hardware support mechanisms for fast synchronization. A Tiered Quiescence Detection Algorithm has been developed which has detection latency that can approach the theoretical minimum of transit time for a single message under appropriate task termination scenarios. For C concurrent tasks on N processors, O(max(C, N)) transmissions are required throughout execution, each of which contains O (log2L) bits if the concurrent tasks are nested L levels deep. A dedicated hardware mechanism was also developed based on this strategy requiring only 3N+2 wires for N PEs.

Sponsors

• UCF Office of Research [Sponsor's Site] [Award Details]
• Harris Computer Systems / Concurrent Computer Corporation, Inc. [Sponsor's Site] [Award Details]
• NCR Corporation [Sponsor's Site] [Award Details]
• State of Florida [Sponsor's Site] [Award Details]

People

Faculty

Publications

Book Chapters

1. R. F. DeMara, Contributor, Comprehensive Dictionary of Electrical Engineering, P. A. Laplante, Editor-in-chief, IEEE Press, 1999, ISBN: 0-8493-3128-5.
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2. R. F. DeMara, "Software Design Guidance Document: Content and Format," IBM FSD Systems Engineering Standards Manual, IBM Corporate Practice CP-2507-014, December 1988, pp. 1 - 18.

Journal Articles

1. Y. Tseng, R. F. DeMara, and A. Ejnioui, "Optimality Analysis of Termination Detection Techniques," submission planned to Parallel Processing Letters.
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2. R. F. DeMara, K. Drake, and A. Ejnioui, "Performance Evaluation of Hierarchical Annotation and Credit Distribution Quiescence Detection Mechanisms," submitted to Distributed Computing on November 20, 2004 and available as UCF Technical Report UCF-ECE-0405
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3. R. F. DeMara, Y. Tseng, and A. Ejnioui, "Tiered Algorithm for Distributed Process Termination Detection," submitted to IEEE Transactions on Parallel and Distributed Systems on September 28, 2004 and available as UCF Technical Report UCF-ECE-0402
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4. R. F. DeMara, Y. Tseng, K. Drake, and A. Ejnioui, “Capability Classes of Barrier Synchronization Techniques,” accepted to International Journal of Computers and Applications on May 10, 2005 and available as UCF Technical Report UCF-ECE-0403
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5. H. A. Bahr and R. F. DeMara, “OTBSAF Scalability on Pentium III/4 and Athlon 64/XP3000 Architectures,” in MSIAC Modeling and Simulation Journal, on February 9, 2005, Vol.6, No. 2, March, 2005, pp. 1 - 4.
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6. H. A. Bahr and R. F. DeMara, “Smart Priority Queue Algorithms for Self-optimizing Event Storage,” Simulation Modeling Practice and Theory, Vol. 12, No. 1, April, 2004, pp. 15 – 40.
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7. Y. Tseng, R. F. DeMara, and P. Wilder, “Distributed-Sum Termination Detection Supporting Multithreaded Execution,” Parallel Computing, Vol. 29, No. 7, July, 2003, pp. 953 – 968.
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8. R. F. DeMara and P. J. Wilder, “A Taxonomy of High Performance Computer Architectures for Uniform Treatment of Multiprocessor Designs,” Computers in Education Journal, Vol. XI, No. 4, October – December, 2001, pp. 45 – 52.
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9. S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson, “Delay-Insensitive Gate-level Pipelining,” Integration, The VLSI Journal, Vol. 30, No. 2, November, 2001, pp. 103 – 131.
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10. B. S. Motlagh and R. F. DeMara, “Performance of Scalable Shared-Memory Architectures,” Journal of Systems, Circuits, and Computers, Vol. 10, No. 1, February, 2000, pp. 1 – 20.
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11. P. J. Wilder and R. F. DeMara, “Rapid-Prototype Microprocessor-based Parallel Architectures,” Journal of Engineering Technology, Vol. 16, No. 1, March, 1999, pp. 24 – 31.
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12. R. F. DeMara, R. Mercer, and M. Ebel, “Helical Latch for Scalable Boolean Logic Operations,” Nanotechnology, Vol. 5, No. 3, July, 1994, pp. 137 – 156.
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13. R. F. DeMara and D. I. Moldovan, “The SNAP-1 Parallel AI Prototype,” IEEE Transactions on Parallel and Distributed Systems, Vol. 4, No. 8, August, 1993, pp. 841 – 854.
    [abstract] [pdf] [bibtex]

Conference Proeedings

1. Y. Tseng and R. F. DeMara, “Communication Pattern based Methodology for Performance Analysis of Termination Detection Schemes,” in Proceedings of the Ninth International Conference on Parallel and Distributed Systems (ICPADS’02), pp. 535 – 541, Chungli Taoyuan, Taiwan, December 17 – 20, 2002.
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2. B. S. Motlagh and R. F. DeMara, “A Scalable Replicated Concurrent-Read Architecture,” in Proceedings of the Fourteenth International Symposium on Computer and Information Sciences (ISCIS'99), Izmir, Turkey, October 18 – 20, 1999.
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3. R. F. DeMara and P. J. Wilder, “A Taxonomy of High Performance Computer Architectures for Uniform Treatment of Multiprocessor Designs,” in Proceedings of the 1999 American Association for Engineering Education Southeastern (ASEE-SE’99) Conference, pp. 1 – 9, Clemson, North Carolina, U.S.A., April 11 – 13, 1999.
   [abstract] [pdf] [doc] [bibtex]
4. R. F. DeMara, H. Zhu, and M. Poston, “Rate Adaptive Source Quench Congestion Avoidance Techniques,” in Proceedings of the 1998 International Symposium on Information Theory and Applications (ISITA’98), pp. 572 – 575, Mexico City, Mexico, October 14 – 16, 1998.
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5. B. S. Motlagh and R. F. DeMara, “Memory Latency in Distributed Shared-Memory Multiprocessors,” in Proceedings of the 1998 IEEE Southeastcon Conference (Southeastcon’98), pp. 134 – 137, Orlando, Florida, U.S.A., April 24 – 26, 1998.
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6. P. J. Wilder, R. F. DeMara, and M. Costello, “Formal Student Presentations: Two views on One Methodology,” in Proceedings of the 1998 American Association for Engineering Education Southeast Section (ASEE-SE’98) Conference, pp. 198 – 200, Orlando, Florida, U.S.A., April 5 – 7, 1998.
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7. S. E. Crawford and R. F. DeMara, “Cache Coherence in Multiport Memory Architecture,” in Proceedings of the Second International Conference on Massively Parallel Computing Systems (MPCS’95), pp. 632 – 642, Ischia, Italy, May 2 – 6, 1995.
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8. R. F. DeMara, B. S. Motlagh, E. Lin, and S. Kuo, “Barrier Synchronization Techniques for Distributed Process Creation,” in Proceedings of the Eighth International Symposium on Parallel Processing (IPPS’94), pp. 597 – 603, Cancun, Mexico, April 26 – 29, 1994.
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9. R. N. Mercer, M. Ebel, and R. F. DeMara, “Pipelined Architecture for Computational Nanotechnology,” in Proceedings of the 1994 IEEE Southcon Conference (Southcon’94), pp. 314 – 319, Orlando, Florida, U.S.A., March 29 – 31, 1994.
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10. R. A. Cagle, R. B. Holl, and R. F. DeMara, “Multifunction Content Addressable Memory for Parallel Speech Understanding,” in Proceedings of the 1994 IEEE Southcon Conference (Southcon’94), pp. 320 – 325, Orlando, Florida, U.S.A., March 29 – 31, 1994.
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11. R. Mercer, M. Ebel, and R. F. DeMara, “Helical Boolean Logic Elements,” in Proceedings of the Third Foresight Conference on Molecular Nanotechnology, Palo Alto, California, U.S.A., October 14 – 16, 1993.
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12. J. D. Roberts, R. F. DeMara, G. Ellis, R. Hughey, R. Levinson, and C. Noshpitz, “AHP: Advanced Hardware for PIERCE,” in Proceedings of the Second International Workshop on PIERCE, pp. 26 – 29, Quebec, Canada, August 7, 1993.
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13. R. F. DeMara and D. I. Moldovan, “Marker-Passing on a Parallel Knowledge Processing Testbed,” in Proceedings of the First International Conference on Parallel and Distributed Information Systems (PDIS’91), pp. 180, Miami, Florida, U.S.A., December 4 – 6, 1991.
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14. R. F. DeMara and D. I. Moldovan, “A DSP Architecture for Parallel AI Processing,” in Proceedings of the 1991 TMS320 Educators Conference, Houston, Texas, U.S.A., July 31 – August 2, 1991.
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15. R. F. DeMara and D. I. Moldovan, “The SNAP-1 Parallel AI Prototype,” in Proceedings of the Eighteenth Annual International Symposium on Computer Architecture (ISCA’91), pp. 2 - 11, Toronto, Ontario, Canada, May 27 - 30, 1991. Also appears in Computer Architecture News, Vol. 19, No. 3, pp. 2 - 11, May, 1991.
    [abstract] [pdf] [bibtex]
16. R. F. DeMara and D. I. Moldovan, “Design of a Clustered Multiprocessor for Real-time Natural Language Understanding,” in Proceedings of the Fifth International Parallel Processing Symposium (IPPS’91), pp. 270 – 277, Anaheim, California, U.S.A., April 30 – May 2, 1991.
    [abstract] [pdf] [bibtex]
17. R. F. DeMara, “Characterizing Marker-Propagation Mechanisms,” in Proceedings of the First Workshop on Abstract Machine Models for Highly Parallel Computers, pp. 77 – 82, Leeds, United Kingdom, March 25 – 27, 1991.
    [abstract] [pdf] [bibtex]